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CS2300-OTP
Fractional-N Clock Multiplier with Internal LCO
Features
Clock Multiplier / Jitter Reduction - Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source
General Description
The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency Synthesizer and a Digital PLL. This architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 Hz. The CS2300-OTP has many configuration options which are set once prior to runtime. At runtime there are three hardware configuration pins available for mode and feature selection. The CS2300-OTP is available in a 10-pin MSOP package in Commercial (-10C to +70C) grade. Customer development kits are also available for custom device prototyping, small production programming, and device evaluation. Please see "Ordering Information" on page 27 for complete details.
Internal LCO Reference Clock Highly Accurate PLL Multiplication Factor - Maximum Error Less Than 1 PPM in HighResolution Mode Configurable Hardware Control Pins Configurable Auxiliary Output No External Analog Loop-filter Components
One-Time Programmability - - -
Minimal Board Space Required
3.3 V
Frequency Reference
Hardware Control
Hardware Configuration
PLL Output Lock Indicator
Auxiliary Output
LCO
Fractional-N Frequency Synthesizer
6 to 75 MHz PLL Output
N
50 Hz to 30 MHz Frequency Reference Output to Input Clock Ratio
Digital PLL & Fractional N Logic
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2008 (All Rights Reserved)
JUN '08 DS844PP1
CS2300-OTP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 4. ARCHITECTURE OVERVIEW ............................................................................................................... 8 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8 4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 8 5. APPLICATIONS ................................................................................................................................... 10 5.1 One Time Programmability ............................................................................................................ 10 5.2 Timing Reference Clock ................................................................................................................. 10 5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 10 5.3.1 CLK_IN Skipping Mode ......................................................................................................... 10 5.3.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 12 5.4 Output to Input Frequency Ratio Configuration ............................................................................. 13 5.4.1 User Defined Ratio (RUD) ..................................................................................................... 13 5.4.2 Manual Ratio Modifier (R-Mod) ............................................................................................. 14 5.4.3 Automatic Ratio Modifier (Auto R-Mod) ................................................................................ 14 5.4.4 Effective Ratio (REFF) .......................................................................................................... 15 5.4.5 Ratio Configuration Summary ............................................................................................... 15 5.5 PLL Clock Output ........................................................................................................................... 16 5.6 Auxiliary Output .............................................................................................................................. 17 5.7 Mode Pin Functionality ................................................................................................................... 17 5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 17 5.7.2 M2 Mode Pin Functionality .................................................................................................... 18 5.7.2.1 M2 Configured as Output Disable .............................................................................. 18 5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 18 5.7.2.3 M2 Configured as Auto R-Mod Enable ...................................................................... 18 5.7.2.4 M2 Configured as AuxOutSrc Override ..................................................................... 18 5.8 Clock Output Stability Considerations ............................................................................................ 19 5.8.1 Output Switching ................................................................................................................... 19 5.8.2 PLL Unlock Conditions .......................................................................................................... 19 6. PARAMETER DESCRIPTIONS ........................................................................................................... 20 6.1 Modal Configuration Sets ............................................................................................................... 20 6.1.1 R-Mod Selection (RModSel[1:0]) ........................................................................................... 20 6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 21 6.1.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 21 6.2 Ratio 0 - 3 ...................................................................................................................................... 21 6.3 Global Configuration Parameters ................................................................................................... 21 6.3.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 21 6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22 6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22 6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 22 6.3.5 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 22 6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 23 7. CALCULATING THE USER DEFINED RATIO .................................................................................... 24 7.1 High Resolution 12.20 Format ....................................................................................................... 24 7.2 High Multiplication 20.12 Format ................................................................................................... 24 8. PROGRAMMING INFORMATION ........................................................................................................ 25 9. PACKAGE DIMENSIONS .................................................................................................................... 26 DS844PP1 2
CS2300-OTP
THERMAL CHARACTERISTICS ......................................................................................................... 26 10. ORDERING INFORMATION .............................................................................................................. 27 11. REVISION HISTORY .......................................................................................................................... 27
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer ....................................................................... 8 Figure 3. Hybrid Analog-Digital PLL ............................................................................................................ 9 Figure 4. External Component Requirements for LCO ............................................................................. 10 Figure 5. CLK_IN removed for > 223 LCO cycles ..................................................................................... 11 Figure 6. CLK_IN removed for < 223 LCO cycles but > tCS ..................................................................... 11 Figure 7. CLK_IN removed for < tCS ........................................................................................................ 12 Figure 8. Low bandwidth and new clock domain ...................................................................................... 12 Figure 9. High bandwidth with CLK_IN domain re-use ............................................................................. 13 Figure 10. Ratio Feature Summary ........................................................................................................... 16 Figure 11. PLL Clock Output Options ....................................................................................................... 16 Figure 12. Auxiliary Output Selection ........................................................................................................ 17 Figure 13. M2 Mapping Options ................................................................................................................ 18 Figure 14. Parameter Configuration Sets .................................................................................................. 20
LIST OF TABLES
Table 1. Modal and Global Configuration .................................................................................................. 10 Table 2. Ratio Modifier .............................................................................................................................. 14 Table 3. Automatic Ratio Modifier ............................................................................................................. 14 Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 15 Table 5. Example 12.20 R-Values ............................................................................................................ 24 Table 6. Example 20.12 R-Values ............................................................................................................ 24
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CS2300-OTP 1. PIN DESCRIPTION
VD GND CLK_OUT AUX_OUT CLK_IN
1 2 3 4 5
10 9 8 7 6
M0 M1 M2 FILTN FILTP
Pin Name
VD GND CLK_OUT AUX_OUT CLK_IN FILTP FILTN M2 M1 M0
#
1 2 3 4 5 6 7 8 9
Pin Description
Digital Power (Input) - Positive power supply for the digital and analog sections. Ground (Input) - Ground reference. PLL Clock Output (Output) - PLL clock output. Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration. Frequency Reference Clock Input (Input) - Clock input for the Digital PLL frequency reference. LCO Filter Connections (Input/Output) - These pins provide external supply filtering for the LCO. Mode Select (Input) - M2 is a configurable mode selection pin. Mode Select (Input) - M1 is a configurable mode selection pin.
10 Mode Select (Input) - M0 is a configurable mode selection pin.
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CS2300-OTP 2. TYPICAL CONNECTION DIAGRAM
0.1 F
1 F
+3.3 V
VD M2 System Microcontroller M1 M0
CS2300-OTP
Frequency Reference CLK_IN FILTP FILTN GND CLK_OUT To circuitry which requires a low-jitter clock To other circuitry or Microcontroller
0.1 F
AUX_OUT
Figure 1. Typical Connection Diagram
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CS2300-OTP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1) Parameters
DC Power Supply Ambient Operating Temperature (Power Applied) Commercial Grade TAC -10 +70 C
Symbol
VD
Min
3.1
Typ
3.3
Max
3.5
Units
V
Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground. Parameters
DC Power Supply Input Current Digital Input Voltage (Note 1) Ambient Operating Temperature (Power Applied) Storage Temperature
Symbol
VD IIN VIN TA Tstg
Min
-0.3 -0.3 -55 -65
Max
6.0 10 VD + 0.4 125 150
Units
V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 1. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10C to +70C (Commercial Grade). Parameters
Power Supply Current - Unloaded Power Dissipation - Unloaded Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -1.2 mA) Low-Level Output Voltage (IOH = 1.2 mA) (Note 2) (Note 2)
Symbol
ID PD IIN IC VIH VIL VOH VOL
Min
70% 80% -
Typ
18 59 8 -
Max
23 76 10 30% 20%
Units
mA mW A pF VD VD VD VD
Notes: 2. To calculate the additional current consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * CL(15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT.
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CS2300-OTP AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10C to +70C (Commercial Grade); CL = 15 pF. Parameters
Clock Input Frequency (Auto R-Mod Disabled) Clock Input Frequency (Auto R-mod Enabled)
Symbol
fCLK_IN fCLK_IN
Conditions
Auto R Modifier = 1 Auto R Modifier = 0.5 Auto R Modifier = 0.25 fCLK_IN < 175 kHz fCLK_IN > 175 kHz (Notes 3, 4) (Note 4) Measured at VD/2 20% to 80% of VD 80% to 20% of VD (Note 5) (Notes 5, 6) (Notes 5, 7)
Min
50 Hz 4 72 168 140 10 20 50 Hz 6 48 -
Typ
50 1.7 1.7 35 50 150 100 1
Max
30 59 138 256 80 75 52 3.0 3.0 110 200 3
Units
MHz kHz kHz kHz ns ns ms kHz MHz % ns ns ps rms ps rms ps rms UI ms
Clock Input Pulse Width Clock Skipping Timeout Clock Skipping Input Frequency PLL Clock Output Frequency PLL Clock Output Duty Cycle Clock Output Rise Time Clock Output Fall Time Period Jitter Base Band Jitter (100 Hz to 40 kHz) Wide Band JItter (100 Hz Corner) PLL Lock Time - CLK_IN (Note 8)
pwCLK_IN tCS fCLK_SKIP fCLK_OUT tOD tOR tOF tJIT
tLC
fCLK_IN < 200 kHz fCLK_IN > 200 kHz
Notes: 3. tCS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequency, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will result in larger values of tCS. 4. Only valid in clock skipping mode; See "CLK_IN Skipping Mode" on page 10 for more information. 5. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11. 6. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 7. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 8. 1 UI (unit interval) corresponds to tCLK_IN or 1/fCLK_IN.
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CS2300-OTP 4. ARCHITECTURE OVERVIEW
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2300 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the LC Oscillator (LCO) by the value of N to generate the PLL output clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 2). The analog PLL based frequency synthesizer uses a low-jitter timing reference clock, the LCO, as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO's control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the VCO output (thus the duty cycle of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies without the need for external filter components.
LC Oscillator
Phase Comparator
Internal Loop Filter
Voltage Controlled Oscillator
PLL Output
Fractional-N Divider
Delta-Sigma Modulator
N
Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer
4.2
Hybrid Analog-Digital Phase Locked Loop
The addition of the Digital PLL and Fractional-N Logic (shown in Figure 3) to the Fractional-N Frequency Synthesizer creates the Hybrid Analog-Digital Phase Locked Loop with many advantages over classical analog PLL techniques. These advantages include the ability to operate over extremely wide frequency ranges without the need to change external loop filter components while maintaining impressive jitter reduction performance. In the Hybrid architecture, the Digital PLL calculates the ratio of the PLL output clock to the frequency reference and compares that to the desired ratio. The digital logic generates a value of N which is then applied to the Fractional-N frequency synthesizer to generate the desired PLL output frequency. Notice that the frequency and phase of the LCO does not affect the output of the PLL since the digital control loop will correct for the PLL output. A major advantage of the Digital PLL is the ease with which the loop filter bandwidth can be altered. The PLL bandwidth is set to a wide-bandwidth mode to quickly achieve lock and then reduced for optimal jitter rejection.
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Delta-Sigma Fractional-N Frequency Synthesizer
LCO
Phase Comparator
Internal Loop Filter
Voltage Controlled Oscillator
PLL Output
Fractional-N Divider
Delta-Sigma Modulator
Digital PLL and Fractional-N Logic
N
Digital Filter
Frequency Reference Clock
Frequency Comparator for Frac-N Generation
Output to Input Ratio for Hybrid mode
Figure 3. Hybrid Analog-Digital PLL
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CS2300-OTP 5. APPLICATIONS
5.1 One Time Programmability
The one time programmable (OTP) circuitry in the CS2300-OTP allows for pre-configuration of the device prior to use in a system. There are two types of parameters that are used for device pre-configuration: modal and global. The modal parameters are features which, when grouped together, create a modal configuration set (see Figure 14 on page 20). Up to four modal configuration sets can be permanently stored and then dynamically selected using the M[1:0] mode select pins (see Table 1). The global parameters are the remaining configuration settings which do not change with the mode select pins. The modal and global parameters can be pre-set at the factory or user programmed using the customer development kit, CDK2000; Please see "Programming Information" on page 25 for more details. Parameter Type
Modal Global
M[1:0] pins = 00
Configuration Set 0 Ratio 0
M[1:0] pins = 01
Configuration Set 1 Ratio 1
M[1:0] pins = 10
Configuration Set 2 Ratio 2
M[1:0] pins = 11
Configuration Set 3 Ratio 3
Configuration settings set once for all modes.
Table 1. Modal and Global Configuration
5.2
Timing Reference Clock
The internal LC oscillator is used to generate the timing reference clock. A single 0.1 F cap must be connected between the FILTP and FILTN pins and FILTN must be connected to ground as shown in Figure 4.
FILTN
FILTP
0.1 F
Figure 4. External Component Requirements for LCO
5.3
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to dynamically generate a fractional-N value for the Frequency Synthesizer (see "Hybrid Analog-Digital PLL" on page 9). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic block then translates the desired ratio based off of CLK_IN to one based off of the internal LCO. This allows the low-jitter internal LCO to be used as the clock which the Frequency Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital PLL. The allowable frequency range for CLK_IN is found in the "AC Electrical Characteristics" on page 7.
5.3.1
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses for up to 20 ms (tCS) at a time (see "AC Electrical Characteristics" on page 7 for specifications). CLK_IN skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn global parameter enables this function.
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Regardless of the setting of the ClkSkipEn parameter the PLL output will continue for 223 LCO cycles (518 ms to 634 ms) after CLK_IN is removed (see Figure 5). This is true as long as CLK_IN does not glitch or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as a change in frequency causing clock skipping and the 223 LCO cycle time-out to be bypassed and the PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 223 LCO cycles pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl parameter; See "PLL Clock Output" on page 16. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified time listed in the "AC Electrical Characteristics" on page 7 after which lock will be acquired and the PLL output will resume.
223 LCO cycles
Lock Time
223 LCO cycles
Lock Time
CLK_IN
ClkSkipEn=0 or 1 ClkOutUnl=0
CLK_IN
ClkSkipEn=0 or 1 ClkOutUnl=1
PLL_OUT UNLOCK
PLL_OUT UNLOCK
= invalid clocks
Figure 5. CLK_IN removed for > 223 LCO cycles f CLK_IN is removed and then reapplied within 223 LCO cycles but later than tCS, the ClkSkipEn parameter will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 6). Once CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl parameter during this time.
tCS Lock Time
223 LCO cycles
223 LCO cycles
tCS Lock Time
CLK_IN
ClkSkipEn=0 or 1 ClkOutUnl=0
CLK_IN
ClkSkipEn=0 or 1 ClkOutUnl=1
PLL_OUT UNLOCK
PLL_OUT UNLOCK
= invalid clocks
Figure 6. CLK_IN removed for < 223 LCO cycles but > tCS If CLK_IN is removed and then re-applied within tCS, the ClkSkipEn parameter determines whether PLL_OUT continues while the PLL re-acquires lock (see Figure 7). When ClkSkipEn is disabled and CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will
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remain continuous throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
tCS tCS Lock Time
CLK_IN
ClkSkipEn=1 ClkOutUnl=0 or 1
CLK_IN
ClkSkipEn=0 ClkOutUnl=1
PLL_OUT UNLOCK
PLL_OUT UNLOCK
= invalid clocks
Lock Time
tCS
CLK_IN
ClkSkipEn=0 ClkOutUnl=0
PLL_OUT UNLOCK
Figure 7. CLK_IN removed for < tCS
Referenced Control Parameter Definition
ClkSkipEn.............................."Clock Skip Enable (ClkSkipEn)" on page 21 ClkOutUnl.............................."Enable PLL Clock Output on Unlock (ClkOutUnl)" on page 22
5.3.2
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2300 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128 Hz using the ClkIn_BW[2:0] global parameter. The minimum loop bandwidth of the Digital PLL directly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL input directly to the PLL output without attenuation. In some applications it is desirable to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the PLL without attenuation. Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other system clocks and associated data are derived will benefit from the maximum jitter and wander rejection of the lowest PLL bandwidth setting. See Figure 8.
CLK_IN
PLL BW = 1 Hz
or
PLL_OUT
Wander and Jitter > 1 Hz Rejected
Wander > 1 Hz
Jitter
MCLK
Subclocks generated from new clock domain.
MCLK LRCK SCLK SDATA D0 D1
LRCK SCLK SDATA D0 D1
Figure 8. Low bandwidth and new clock domain Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the system. See Figure 9. If there is substantial wander on the CLK_IN signal in these applications, it may be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT 12 DS844PP1
CS2300-OTP
signal in order to maintain phase alignment. For these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those synchronous to the PLL_OUT domain.
CLK_IN
PLL BW = 128 Hz
or
PLL_OUT
Jitter > 128 Hz Rejected Wander < 128 Hz Passed to Output
Wander < 128 Hz
Jitter
MCLK
MCLK LRCK SCLK SDATA D0 D1
Subclocks and data re-used from previous clock domain.
LRCK SCLK SDATA D0 D1
Figure 9. High bandwidth with CLK_IN domain re-use While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] parameter.
Referenced Control Parameter Definition ClkIn_BW[2:0] ......................."Clock Input Bandwidth (ClkIn_BW[2:0])" on page 23
5.4 5.4.1
Output to Input Frequency Ratio Configuration User Defined Ratio (RUD)
The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2300's one time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select pins. The 32-bit RUD can be expressed in either a high resolution (12.20) or high multiplication (20.12) format selectable by the LFRatioCfg global parameter. The RUD for high resolution (12.20) format is encoded with 12 MSBs representing the integer binary portion with the remaining 20 LSBs representing the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See "Calculating the User Defined Ratio" on page 24 for more information. The RUD for high multiplication (20.12) format is encoded with 20 MSBs representing the integer binary portion with the remaining 12 LSBs representing the fractional binary portion. In this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM. It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the timing reference clock and the resolution of the RUD.
Referenced Control
Parameter Definition
Ratio 0-3................................"Ratio 0 - 3" on page 21 LFRatioCfg ............................"Low-Frequency Ratio Configuration (LFRatioCfg)" on page 22 M[1:0] ...................................."M1 and M0 Mode Pin Functionality" on page 17
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5.4.2 Manual Ratio Modifier (R-Mod)
The manual Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio0-3 stored in the register space remain unchanged). The available options for R-Mod are summarized in Table 2 on page 14. R-Mod is enabled via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page 18). RModSel[1:0] 00 01 10 11 R Modifier 0.5 0.25 0.125 0.0625 Table 2. Ratio Modifier
Referenced Control Parameter Definition Ratio 0-3................................"Ratio 0 - 3" on page 21 RModSel[1:0] ........................"R-Mod Selection (RModSel[1:0])" section on page 20 M2Config[2:0]........................"M2 Pin Configuration (M2Config[2:0])" on page 22
5.4.3
Automatic Ratio Modifier (Auto R-Mod)
The Automatic R-Modifier uses the CLK_IN Frequency Range Detector to implement a frequency dependent multiply of the currently addressed RUD as shown in Table 3. The CLK_IN Frequency Range Detector determines the ratio between the frequency of the internal SysClk and the CLK_IN input signal. The result of the ratio measurement is the internal status signal called FsDetect[1:0]. Like with R-Mod, the Ratio0-3 parameters stored in the one time programmable memory remain unchanged. The Automatic Ratio Modifier is enabled either by the AutoRMod modal parameter or via the M2 pin in conjunction with the appropriate setting of the M2Config[2:0] global parameter (see Section 5.7.2 on page 18). FsDetect[1:0]
00 01 10
fSysClk / fCLK_IN
> 224 96 - 224 < 96
Auto R Modifier
1 0.5 0.25
Table 3. Automatic Ratio Modifier It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected by the RModSel[1:0] modal parameter and is used to calculate the Effective Ratio (see Section 5.4.4 on page 15). Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A converters. For example, if the clock applied to CLK_IN is the audio sample rate, Fs (also known as the word, frame or Left/Right clock), SysClk is the internal LCO (between 13.23 MHz and 16.17 MHz), FsDe-
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tect[1:0] would then reflect the frequency range of the audio sample rate. An RUD of 512 generates the audio oversampling clocks as shown in Table 4. Speed Mode (used for audio converters)
Single Speed Double Speed
FsDetect[1:0]
00 01
Inferred Audio Sample Rate
< [59 to 72] kHz >[59 to 72] kHz and <[138 to 168] kHz > [138 to 168] kHz
Audio Oversampling Clock
512 x 256 x
10
Quad Speed
128 x
Table 4. Example Audio Oversampling Clock Generation from CLK_IN
Referenced Control Parameter Definition Ratio 0-3................................"Ratio 0 - 3" on page 21 RModSel[1:0] ........................"R-Mod Selection (RModSel[1:0])" section on page 20 AutoRMod ............................."Auto R-Modifier Enable (AutoRMod)" on page 21 M2Config[2:0]........................"M2 Pin Configuration (M2Config[2:0])" on page 22
5.4.4
Effective Ratio (REFF)
The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as previously described. REFF is calculated as follows: REFF = RUD * R-Mod * Auto R-Mod Ratio modifiers which would produce an overflow or truncation of REFF should not be used. In all cases, the maximum and minimum allowable values for REFF are dictated by the frequency limits for both the input and output clocks as shown in the "AC Electrical Characteristics" on page 7. Selection of the user defined ratio from the four stored ratios is made by using the M[1:0] pins.
Referenced Control Parameter Definition M[1:0] pins............................."M1 and M0 Mode Pin Functionality" on page 17
5.4.5
Ratio Configuration Summary
The RUD is the user defined ratio for which up to four different values (Ratio0-3) can be stored in the one time programmable memory. The M[1:0] pins then select the user defined ratio to be used as well as the modal configuration set. The resolution/format for the RUD is selectable. R-Mods are applied according to their settings. The user defined ratio, ratio modifier, and automatic ratio modifier make up the effective
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ratio REFF, the final calculation used to determine the output to input clock ratio. The conceptual diagram in Figure 10 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer. The subscript `4' indicates the modal parameters.
Effective Ratio REFF M[1:0] pins User Defined Ratio RUD Ratio 0 Ratio 1 Ratio 2 Ratio 3 LFRatioCfg AutoRMod4 or M2 pin FsDet[1:0] Frequency Reference Clock (CLK_IN) Ratio Format 12.20 20.12 Ratio Modifier Auto R-Mod M2 pin RModSel[1:0]4 Dynamic Ratio, `N' LCO
Frequency Synthesizer
Digital PLL & Fractional N Logic
PLL Output
Figure 10. Ratio Feature Summary
Referenced Control Parameter Definition Ratio 0-3................................"Ratio 0 - 3" on page 21 M[1:0] pins............................."M1 and M0 Mode Pin Functionality" on page 17 LFRatioCfg ............................"Low-Frequency Ratio Configuration (LFRatioCfg)" on page 22 RModSel[1:0] ........................"R-Mod Selection (RModSel[1:0])" section on page 20 AutoRMod ............................."Auto R-Modifier Enable (AutoRMod)" on page 21
5.5
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the M2 pin when the M2Config[1:0] global parameter is set to either 000 or 010. The output from the PLL automatically drives a static low condition while the PLL is unlocked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl global parameter, however the state CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl PLL Locked/Unlocked 0
0
2:1 Mux
1
M2 pin with M2Config[1:0] = 000, 010 0 PLL Clock Output PLLClkOut
2:1 Mux
PLL Output 1
PLL Clock Output Pin (CLK_OUT)
Figure 11. PLL Clock Output Options
Referenced Control Parameter Definition ClkOutUnl.............................."Enable PLL Clock Output on Unlock (ClkOutUnl)" on page 22 ClkOutDis .............................."M2 Configured as Output Disable" on page 18 M2Config[2:0]........................"M2 Pin Configuration (M2Config[2:0])" on page 22
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5.6 Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 12, to one of three signals: input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] modal parameter. If AUX_OUT is set to Lock, the AuxLockCfg global parameter is then used to control the output driver type and polarity of the LOCK signal (see section 6.3.2 on page 22). If AUX_OUT is set to CLK_OUT, the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the M2 pin when the M2Config[1:0] global parameter is set to either 001 or 010.
AuxOutSrc[1:0]
Frequency Reference Clock (CLK_IN)
M2 pin with M2Config[1:0] = 001, 010
PLL Clock Output (PLLClkOut)
3:1 Mux
Auxiliary Output Pin (AUX_OUT)
PLL Lock/Unlock Indication (Lock)
AuxLockCfg
Figure 12. Auxiliary Output Selection
Referenced Control Parameter Definition AuxOutSrc[1:0]......................"Auxiliary Output Source Selection (AuxOutSrc[1:0])" on page 21 AuxOutDis ............................."M2 Configured as Output Disable" on page 18 AuxLockCfg..........................."AUX PLL Lock Output Configuration (AuxLockCfg)" section on page 22 M2Config[2:0]........................"M2 Pin Configuration (M2Config[2:0])" on page 22
5.7 5.7.1
Mode Pin Functionality M1 and M0 Mode Pin Functionality
M[1:0] determine the functional mode of the device and select both the default User Defined Ratio and the set of modal parameters. The modal parameters are RModSel[1:0], AuxOutSrc[1:0], and AutoRMod. By modifying one or more of the modal parameters between the 4 sets, different functional configurations can be achieved. However, global parameters are fixed and the same value will be applied to each functional configuration. Figure 14 on page 20 provides a summary of all parameters used by the device.
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5.7.2 M2 Mode Pin Functionality
M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. Depending on what M2 is mapped to, it will either act as an output enable/disable pin or override certain modal parameters. Figure 13 summarizes the available options and the following sections will describe each option in more detail.
M2Config[2:0] global parameter
000 001 010 011 M2 pin 100 101 110 111
Disable CLK_OUT pin Disable AUX_OUT pin Disable CLK_OUT and AUX_OUT pins RModSel[1:0] Modal Parameter Enable Reserved AutoRMod Modal Parameter Override Reserved Force AuxOutSel[1:0] = 10 (PLL Clock Out)
Figure 13. M2 Mapping Options
5.7.2.1
M2 Configured as Output Disable
If M2Config[2:0] is set to either `000', `001', or `010', M2 becomes an output disable pin for one or both output pins. If M2 is driven `low', the corresponding output(s) will be enabled, if M2 is driven `high', the corresponding output(s) will be disabled.
5.7.2.2
M2 Configured as R-Mod Enable
If M2Config[2:0] is set to `011', M2 becomes the R-Mod enable pin. It should be noted that M2 is the only way to enable R-Mod. Even though the RModSel[1:0] modal parameter can be set arbitrarily for each configuration set, it will not take effect unless enabled via M2. If M2 is driven `low', R-Mod will be disabled, if M2 is driven `high' R-Mod will be enabled.
5.7.2.3
M2 Configured as Auto R-Mod Enable
If M2Config[2:0] is set to `101', M2 becomes the Auto R-Mod enable pin and will override the AutoRMod modal parameter. If M2 is driven `low', Auto R-Mod will be disabled, if M2 is driven `high' Auto R-Mod will be enabled.
5.7.2.4
M2 Configured as AuxOutSrc Override
If M2Config[2:0] is set to `111', M2 when driven `high' will override the AuxOutSrc[1:0] modal parameter and force the AUX_OUT source to PLL Clock Output. When M2 is driven `low', AUX_OUT will function according to AuxOutSrc[1:0].
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5.8 5.8.1 Clock Output Stability Considerations Output Switching
The CS2300-OTP is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist: * * Enabling/disabling AUX_OUT when AuxOutSrc = 11 (unlock indicator). Switching AuxOutSrc[1:0] to or from 01 (CLK_IN) and to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch).
When any of these exceptions occur, a partial clock period on the output may result.
5.8.2
PLL Unlock Conditions
Certain changes to the clock inputs and mode pins can cause the PLL to lose lock which will affect the presence of a clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked: * * * Any change in the state of the M1 and M0 pins will cause the PLL to temporarily lose lock as the new setting takes affect. Changes made to the state of the M2 when the M2Config[2:0] global parameter is set to 011, 100, 101, or 110 can cause the PLL to temporarily lose lock as the new setting takes affect. Discontinuities on the Frequency Reference Clock, CLK_IN, except when the Clock Skipping feature is enabled and the requirements of Clock Skipping are satisfied (see "CLK_IN Skipping Mode" on page 10). Gradual changes in CLK_IN frequency greater than 30% from the starting frequency. Step changes in CLK_IN frequency.
* *
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CS2300-OTP 6. PARAMETER DESCRIPTIONS
As mentioned in Section 5.1 on page 10, there are two different kinds of parameter configuration sets, Modal and Global. These configuration sets, shown in Figure 14, can be programmed in the field using the CDK2000 or preprogrammed at the factory. Please see "Programming Information" on page 25 for more details.
M[1:0] pins
Modal Configuration Set #0 Ratio 0 RModSel[1:0] AuxOutSrc[1:0] AutoRmod
00
Modal Configuration Set #1
Modal Configuration Set #2 Ratio 2 RModSel[1:0] AuxOutSrc[1:0] AutoRmod
10
Modal Configuration Set #3 Ratio 3 RModSel[1:0] AuxOutSrc[1:0] AutoRmod
11
Global Configuration Set ClkSkipEn AuxLockCfg ClkOutUnl LFRatioCfg M2Config[2:0] ClkIn_BW[2:0]
Figure 14. Parameter Configuration Sets
6.1
Modal Configuration Sets
There are four instances of each of these configuration parameters. Selection between the four stored sets is made using the M[1:0] pins.
6.1.1
R-Mod Selection (RModSel[1:0])
Selects the R-Mod value, which is used as a factor in determining the PLL's Fractional N.
RModSel[1:0] 00 01 10 11 Application: R-Mod Selection Right-shift R-value by 1 (/ 2). Right-shift R-value by 2 (/ 4). Right-shift R-value by 3 (/ 8). Right-shift R-value by 4 (/ 16). "Manual Ratio Modifier (R-Mod)" on page 14
Note: This parameter does not take affect unless M2 pin is high and the M2Config[2:0] global parameter is set to `011'.
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Ratio 1
RModSel[1:0]
AuxOutSrc[1:0]
AutoRmod
01
CS2300-OTP
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0] 00 01 10 11 Application: Auxiliary Output Source Reserved. CLK_IN. CLK_OUT. PLL Lock Status Indicator. "Auxiliary Output" on page 17
Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type ("AUX PLL Lock Output Configuration (AuxLockCfg)" on page 22).
6.1.3
Auto R-Modifier Enable (AutoRMod)
Controls the automatic ratio modifier function.
AutoRMod 0 1 Application: Automatic R-Mod State Disabled. Enabled. "Automatic Ratio Modifier (Auto R-Mod)" on page 14
6.2
Ratio 0 - 3
The four 32-bit User Defined Ratios are stored in the CS2300's one time programmable memory. See "Output to Input Frequency Ratio Configuration" on page 13 and "Calculating the User Defined Ratio" on page 24 for more details.
6.3 6.3.1
Global Configuration Parameters Clock Skip Enable (ClkSkipEn)
This parameter enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the CLK_IN has missing pulses.
ClkSkipEn 0 1 Application: PLL Clock Skipping Mode Disabled. Enabled. "CLK_IN Skipping Mode" on page 10
Note:
fCLK_IN must be < 80 kHz to use this feature.
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6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = `11'), this global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is disregarded.
AuxLockCfg 0 1 Application: AUX_OUT Driver Configuration Push-Pull, Active High (output `high' for unlocked condition, `low' for locked condition). Open Drain, Active Low (output `low' for unlocked condition, high-Z for locked condition). "Auxiliary Output" on page 17
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. Therefore, the pin polarity is defined relative to the unlock condition.
6.3.3
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl 0 1 Application: Clock Output Enable Status Clock outputs are driven `low' when PLL is unlocked. Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). "PLL Clock Output" on page 16
6.3.4
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio .
LFRatioCfg 0 1 Application: Ratio Bit Encoding Interpretation 20.12 - High Multiplier. 12.20 - High Accuracy. "User Defined Ratio (RUD)" on page 13
6.3.5
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin.
M2Config[2:0] 000 001 010 011 100 101 110 111 Application: M2 pin function Disable CLK_OUT pin. Disable AUX_OUT pin. Disable CLK_OUT and AUX_OUT. RModSel[1:0] Modal Parameter Enable. Reserved. AutoRMod Modal Parameter Override. Reserved. Force AuxOutSrc[1:0] = 10 (PLL Clock Out). "M2 Mode Pin Functionality" on page 18
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6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0] 000 001 010 011 100 101 110 111 Application: Minimum Loop Bandwidth 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz "Adjusting the Minimum Loop Bandwidth for CLK_IN" on page 12
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CS2300-OTP 7. CALCULATING THE USER DEFINED RATIO
Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who would like to know more about how the User Defined Ratio is calculated and stored.
Most calculators do not interpret the fixed point binary representation which the CS2300-OTP uses to define the output to input clock ratio (see Section 5.4.1 on page 13); However, with a simple conversion we can use these tools to generate a binary or hex value for Ratio0-3 to be stored in one time programmable memory. Please see "Programming Information" on page 25 for more details on programming.
7.1
High Resolution 12.20 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 220 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 5. Desired Output to Input Clock Ratio (output clock/input clock)
12.288 MHz/10 MHz=1.2288 11.2896 MHz/44.1 kHz=256
Scaled Decimal Representation = (output clock/input clock) * 220 1288490 268435456
Hex Representation of Binary RUD 00 13 A9 2A 10 00 00 00
Table 5. Example 12.20 R-Values
7.2
High Multiplication 20.12 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 212 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 6. Desired Output to Input Clock Ratio (output clock/input clock)
12.288 MHz/60 Hz=204,800 11.2896 MHz/59.97 Hz =188254.127...
Scaled Decimal Representation = (output clock/input clock) * 212 838860800 771088904
Hex Representation of Binary RUD 32 00 00 00 2D F5 E2 08
Table 6. Example 20.12 R-Values
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CS2300-OTP 8. PROGRAMMING INFORMATION
Field programming of the CS2300-OTP is achieved using the hardware and software tools included with the CDK2000. The software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a CDK. The CDK2000 is designed with built-in features to ease the process of programming small quantities of devices for prototype and small production builds. In addition to its field programming capabilities, the CDK2000 can also be used for the complete evaluation of programmed CS2300-OTP devices. The CS2300-OTP can also be factory programmed for large quantity orders. When ordering factory programmed devices, the CDK should first be used to program and evaluate the desired configuration. When evaluation is complete, the CS2000 Configuration Wizard is used to generate a file containing all device configuration information; this file is conveyed to Cirrus Logic as a complete specification for the factory programming configuration. Please contact your local Cirrus Logic sales representative for more information regarding factory programmed parts. See the CDK2000 datasheet, available at www.cirrus.com, for detailed information on the use of the CDK2000 programming and evaluation tools. Below is a form which represents the information required for programming a device (noted in gray). The "Parameter Descriptions" section beginning on page 20 describes the functions of each parameter. This form may be used either for personal notation for device configuration or it can be filled out and given to a Cirrus representative in conjunction with the programming file from the CDK2000 as an additional check. The User Defined Ratio may be filled out in decimal or it may be entered as hex as outlined in "Calculating the User Defined Ratio" on page 24. For all other parameters mark a `0' or `1' below the parameter name.
OTP Modal and Global Configuration Parameters Form Modal Configuration Set #0 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #1 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #2 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Modal Configuration Set #3 Ratio 0 (dec) Ratio 0 (hex) __ __ : __ __ : __ __ : __ __ RModSel1 RModSel0 AuxOutSrc1 AuxOutSrc0 Global Configuration Set ClkSkipEn AuxLockCfg ClkIn_BW2 ClkIn_BW1
AutoRMod
AutoRMod
AutoRMod
AutoRMod
ClkOutUnl ClkIn_BW0
LFRatioCfg
M2Cfg2
M2Cfg1
M2Cfg0
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CS2300-OTP 9. PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
N
D c E A2 A1
L
E11 A
e b END VIEW SIDE VIEW SEATING PLANE
L1
123
TOP VIEW
DIM
A A1 A2 b c D E E1 e L L1
MIN
-0 0.0295 0.0059 0.0031 ----0.0157 --
INCHES NOM
-----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF
MAX
0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 --
MIN
-0 0.75 0.15 0.08 ----0.40 --
MILLIMETERS NOM
-----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF
NOTE MAX
1.10 0.15 0.95 0.30 0.23 ----0.80 --
4, 5 2 3
Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer
Symbol
JA JA
Min
-
Typ
170 100
Max
-
Units
C/W C/W
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CS2300-OTP 10.ORDERING INFORMATION
The CS2300-OTP is ordered as an un-programmed device. The CS2300-OTP can also be factory programmed for large quantity orders. Please see "Programming Information" on page 25 for more details.
Product
CS2300-OTP CS2300-OTP CDK2000
Description
Clocking Device Clocking Device Evaluation Platform
Package
10L-MSOP 10L-MSOP -
Pb-Free Yes Yes Yes
Grade Commercial -
Temp Range Container
-10 to +70C -10 to +70C Rail Tape and Reel -
Order# CS2300P-CZZ CS2300P-CZZR CDK-2000-LCO
11.REVISION HISTORY
Release
A1 PP1 Initial Release Updated "AC Electrical Characteristics" on page 7
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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